CD74HCT86 - High-Speed CMOS Logic ...

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//-->CD54HC86, CD74HC86,CD54HCT86, CD74HCT86Data sheet acquired from Harris SemiconductorSCHS137DAugust 1997 - Revised September 2003High-Speed CMOS LogicQuad 2-Input EXCLUSIVE-OR GateDescriptionThe ’HC86 and ’HCT86 contain four independentEXCLUSIVE OR gates in one package. They provide thesystem designer with a means for implementation of theEXCLUSIVE OR function. Logic gates utilize silicon gateCMOS technology to achieve operating speeds similar toLSTTL gates with the low power consumption of standardCMOS integrated circuits. All devices have the ability to drive10 LSTTL loads. The HCT logic family is functionally pincompatible with the standard LS logic family.Features[ /Title(CD74HC86,CD74HCT86)/Sub-ject(HighSpeedCMOSLogicQuad2-InputEXCLUSIVEOR• Typical Propagation Delay: 9ns at VCC= 5V,CL= 15pF, TA= 25oC• Fanout (Over Temperature Range)- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads• Wide Operating Temperature Range . . . -55oC to 125oC• Balanced Propagation Delay and Transition Times• Significant Power Reduction Compared to LSTTLLogic ICs• HC Types- 2V to 6V Operation- High Noise Immunity: NIL= 30%, NIH= 30% of VCCat VCC= 5V• HCT Types- 4.5V to 5.5V Operation- Direct LSTTL Input Logic Compatibility,VIL= 0.8V (Max), VIH= 2V (Min)- CMOS Input Compatibility, Il≤1µA at VOL, VOHOrdering InformationPART NUMBERCD54HC86F3ACD54HCT86F3ACD74HC86ECD74HC86MCD74HC86MTTEMP. RANGE(oC)-55 to 125-55 to 125-55 to 125-55 to 125-55 to 125-55 to 125-55 to 125-55 to 125-55 to 125-55 to 125PACKAGE14 Ld CERDIP14 Ld CERDIP14 Ld PDIP14 Ld SOIC14 Ld SOIC14 Ld SOIC14 Ld PDIP14 Ld SOIC14 Ld SOIC14 Ld SOICApplications• Logical Comparators• Parity Generators and Checkers• Adders and SubtractorsCD74HC86M96CD74HCT86ECD74HCT86MCD74HCT86MTCD74HCT86M96NOTE: When ordering, use the entire part number. The suffix 96denotes tape and reel. The suffix T denotes a small-quantity reel of250.PinoutCD54HC86, CD54HCT86(CERDIP)CD74HC86, CD74HCT86(PDIP, SOIC)TOP VIEW1A 11B 21Y 32A 42B 52Y 6GND 714 VCC13 4B12 4A11 4Y10 3B9 3A8 3YCAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.Copyright©2003, Texas Instruments Incorporated1CD54HC86, CD74HC86, CD54HCT86, CD74HCT86Functional Diagram11A21B1Y2A2B2YGND34567124A114Y103B93A83Y134B14VCCTRUTH TABLEINPUTSnALLHHnBLHLHOUTPUTnYLHHLH = High Voltage Level, L = Low Voltage LevelLogic SymbolnAnYnB2CD54HC86, CD74HC86, CD54HCT86, CD74HCT86Absolute Maximum RatingsDC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7VDC Input Diode Current, IIKFor VI< -0.5V or VI> VCC+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mADC Output Diode Current, IOKFor VO< -0.5V or VO> VCC+ 0.5V. . . . . . . . . . . . . . . . . . . .±20mADC Output Source or Sink Current per Output Pin, IOFor VO> -0.5V or VO< VCC+ 0.5V. . . . . . . . . . . . . . . . . . . .±25mADC VCCor Ground Current, ICC orIGND. . . . . . . . . . . . . . . . . .±50mAThermal InformationThermal Resistance (Typical, Note 1)θJA(oC/W)E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . .80M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . .86Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oCMaximum Storage Temperature Range . . . . . . . . . .-65oC to 150oCMaximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC(SOIC - Lead Tips Only)Operating ConditionsTemperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oCSupply Voltage Range, VCCHC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6VHCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5VDC Input or Output Voltage, VI, VO. . . . . . . . . . . . . . . . . 0V to VCCInput Rise and Fall Time2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationof the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.NOTE:1. The package thermal impedance is calculated in accordance with JESD 51-7.DC Electrical SpecificationsTESTCONDITIONSPARAMETERHC TYPESHigh Level InputVoltageVIH--24.56Low Level InputVoltageVIL--24.56High Level OutputVoltageCMOS LoadsHigh Level OutputVoltageTTL LoadsLow Level OutputVoltageCMOS LoadsLow Level OutputVoltageTTL LoadsInput LeakageCurrentQuiescent DeviceCurrentIIICCVCCorGNDVCCorGNDVOLVIHorVILVOHVIHorVIL-0.02-0.02-0.02-4-5.20.020.020.0245.2-24.564.5624.564.56661.53.154.2---1.94.45.93.985.48----------------------------0.51.351.8-----0.10.10.10.260.26±0.121.53.154.2---1.94.45.93.845.34----------0.51.351.8-----0.10.10.10.330.33±1201.53.154.2---1.94.45.93.75.2----------0.51.351.8-----0.10.10.10.40.4±140VVVVVVVVVVVVVVVVµAµASYMBOLVI(V)IO(mA) VCC(V)MIN25oCTYPMAX-40oC TO +85oCMINMAX-55oC TO 125oCMINMAXUNITS3CD54HC86, CD74HC86, CD54HCT86, CD74HCT86DC Electrical Specifications(Continued)TESTCONDITIONSPARAMETERHCT TYPESHigh Level InputVoltageLow Level InputVoltageHigh Level OutputVoltageCMOS LoadsHigh Level OutputVoltageTTL LoadsLow Level OutputVoltageCMOS LoadsLow Level OutputVoltageTTL LoadsInput LeakageCurrentQuiescent DeviceCurrentAdditional QuiescentDevice Current PerInput Pin: 1 Unit LoadNOTE:2. For dual-supply systems theoretical worst case (VI= 2.4V, VCC= 5.5V) specification is 1.8mA.IIVCCandGNDVCCorGNDVCC- 2.1VOLVIHorVILVIHVILVOH--VIHorVIL---0.024.5 to5.54.5 to5.54.52-4.4----0.8-2-4.4-0.8-2-4.4-0.8-VVVSYMBOLVI(V)IO(mA) VCC(V)MIN25oCTYPMAX-40oC TO +85oCMINMAX-55oC TO 125oCMINMAXUNITS-44.53.98--3.84-3.7-V0.024.5--0.1-0.1-0.1V44.5--0.26-0.33-0.4V-5.5-±0.1-±1-±1µAICC∆ICC(Note 2)-5.54.5 to5.5---1002360--20450--40490µAµAHCT Input Loading TableINPUTAllUNIT LOADS1NOTE: Unit Load is∆ICClimit specified in DC ElectricalSpecifications table, e.g. 360µA max at 25oC.Switching SpecificationsPARAMETERHC TYPESPropagation Delay,Input toOutput (Figure 1)Input tr, tf= 6nsTESTCONDITIONSVCC(V)25oCMINTYPMAX-40oC TO 85oC -55oC TO 125oCMINMAXMINMAXUNITSSYMBOLtPLH, tPHLCL= 50pF24.56-----------9----1202420-75151310--------1503026-95191610--------1803631-110221910nsnsnsnsnsnsnspFPropagation Delay, Data Input toOutput YTransition Times (Figure 1)tPLH, tPHLtTLH, tTHLCL= 15pFCL= 50pF524.56Input CapacitanceCI--4CD54HC86, CD74HC86, CD54HCT86, CD74HCT86Switching SpecificationsPARAMETERPower Dissipation Capacitance(Notes 3, 4)HCT TYPESPropagation Delay, Input toOutput (Figure 2)Propagation Delay, Data Input toOutput YTransition Times (Figure 2)Input CapacitancePower Dissipation Capacitance(Notes 3, 4)NOTES:3. CPDis used to determine the dynamic power consumption, per gate.4. PD= VCC2fi(CPD+ CL) where fi= input frequency, CL= output load capacitance, VCC= supply voltage.tPLH, tPHLtPLH, tPHLtTLH, tTHLCICPDCL= 50pFCL= 15pFCL= 50pF--4.554.5-5------13--2732-1510------40-1910------48-2210-nsnsnspFpFInput tr, tf= 6ns(Continued)TESTCONDITIONS-VCC(V)525oCMIN-TYP22MAX--40oC TO 85oC -55oC TO 125oCMIN-MAX-MIN-MAX-UNITSpFSYMBOLCPDTest Circuits and Waveformstr= 6nsINPUT90%50%10%tTLH90%50%10%tPHLtPLHtf= 6nsVCCINPUTGNDtTHLtr= 6ns2.7V1.3V0.3VtTLH90%INVERTINGOUTPUTtPHLtPLH1.3V10%tf= 6ns3VGNDtTHLINVERTINGOUTPUTFIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGA-TION DELAY TIMES, COMBINATION LOGICFIGURE 2. HCT TRANSITION TIMES AND PROPAGATIONDELAY TIMES, COMBINATION LOGIC5 [ Pobierz całość w formacie PDF ]